Chinese Memory, Kioxia, Micron, Xilinx And SDC

Lots of news on memory topics today.  We will discuss DRAM production plans in China, Toshiba Memory’s change to Kioxia, a Micron and Xilinx collaboration and several memory oriented talks from the 2019 SNIA Storage Developers Conference.

According to Jim Handy of Objective Analysis, with an investment of over $150 billion China has shown its determination to become self-sufficient in memory chips, and is most likely to achieve its goals.  One of these memory initiatives is CXMT (ChangXin Memory Technology).  CXMT was established in 2016, extending and developing upon technology acquired from Qimonda.   

CXMT gave a talk on DRAM Technology Trend and Industrial Applications at the China Flash Market Summit in late September.  According to the talk by Dr. Ping from CXMT, CXMT is the first Chinese DRAM IDM (Integrated Device Manufacturer) to move into the production phase and has pushed the original 46nm DRAM of Quimonda to the 10nm-scale using advanced fabrication tools such as EUV and HKMG (high dielectric constant (k) metal gate) as shown in the slide from the presentation below.

Toshiba Memory Corporation was officially renamed Kioxia Holdings Corporation, showing its independence from its former parent, Toshiba.  Earlier in September 2019 the company made an offer to purchase Taiwan’s LITE-ON’s solid state drive business for $165M.  Toshiba will own the LITE-ON SSD brands and operations, assets including equipment, workers, intellectual property, technology, client and supplier relationships and inventories, and gets access to its channels. These include LITE-ON's relationships with PC suppliers such as Dell.

Micron announced that it is working with Xilinx to boost the boot and dynamic configuration performance of Xilinx’s Versal™ platform, what it calls an adaptive compute acceleration platform (ACAP). ACAP is a new category of heterogeneous compute devices that Micxorn says will  use Micron Xccela™ flash and other Micron memory solutions to reduce system startup times and increase system responsiveness in automotive, industrial, networking and consumer applications that use artificial intelligence (AI).

According to Xilinx, its Versal ACAP is built for AI inference in emerging applications of data center, automotive, 5G infrastructure, aerospace, defense, and test and measurement. Using the Xccela bus interface, a JEDEC xSPI-compliant standard developed and promoted by the Xccela Consortium(https://www.xccela.org/technology/), Xilinx Versal ACAP increases boot and configuration performance by eight times, compared to prior-generation FPGA platforms using quad serial peripheral interface (SPI) NOR flash. Xccela flash delivers up to 400 megabytes per second in double data rate mode while consuming 30% less effective energy per bit over traditional quad SPI NOR flash.

At the 2019 SNIA Storage Developers Conference (SDC) in Santa Clara there were several talks on developing memory technologies.  A company called MemVerge spoke on storage defined memory technology, especially focused on DDR-based 3D XPoint technology (such as Intel’s Optane DC Persistent Memory).  The company has developed a memory “hypervisor” that the company says allows them to deliver larger memory and faster storage to applications without application rewrites. The figure below shows how this can be applied to various application coordinating DRAM, storage class (or persistent) memory and SSDs at various computing nodes.

Also at the 2019 SDC Usha Upadhyayula from Intel spoke about how Intel’s Optane DC Persistent Memory can be used for volatile and non-volatile applications as shown below. Intel has made a unified memory management software called libmemkind (available in github) that can manage DRAM, High BW Memory (HBM) and Intel’s Optane DC Persistent Memory that acts as an API.

At the 2019 SDC Steffen Hellmold from Western Digital spoke about Zoned Namespace memory (also a topic of other talks and exhibits at the show).  He pointed out that much of future data center storage will be on shingled hard disk drives and that these HDDs consist of zones in which the written tracks are overlapped and within each zone only sequential writes are allowed.  Similarly, NAND die are composed of erase blocks consisting of several pages.  Within the erase blocks pages are usually written sequentially as well.  This has led to a zoned access architecture, as show below.

Steffen also discussed Western Digital’s plan to introduced open source RISC-V cores in their storage products (RISC-V SweRV core) and it advocacy of a memory fabric technology called OmniXtend (also available on github).

Memory technology drives computer applications.  New developments, particularly the move from volatile to non-volatile memory could change the capacity, management and uses for memory technology and computer architectures.